View AD9648_3702413.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 4 - bit, 125 msps /105 msps, 1.8 v dual analog- to - digital converter AD9648 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assume d by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or pate nt rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fa x: 781.461.3113 ? 2011 analog devices, inc. all rights reserved. features 1.8 v analog supply operation 1.8 v cmos or lvds outputs snr = 7 4 . 5 dbfs @ 70 mhz sfdr = 91 dbc @ 70 mhz low power: 78 mw /channel adc core @ 125 msps differential analog input with 650 mhz bandwidth if samp ling frequenc ies to 2 0 0 mhz on - chip volta ge reference and sample - and - hold circuit 2 v p - p differential analog input dnl = 0.3 5 lsb serial port control options offset binary, gray code, or twos complement data format optional clock duty cycle stabilizer integer 1 - to - 8 input clock divider data out put multiplex option built - in selectable digital test pattern generation energy - saving power - down modes data clock out with programmable clock and data alignment applications communications diversity radio systems multimode digital receivers gsm, edge, w - cdma, lt e, cdma2000, wimax , td - scdma i/q demodulation systems smart antenna systems broadband data applications battery - powered instruments hand held scope meters portable medical imaging ultrasound radar/lidar 1 this product is protect ed by a u.s p aten t. functional block dia gram vin+ a vin? a vref sense vcm rbias vin?b vin+b or a d0 a d13 a dco a dr vdd orb d13b d0b dcob sdio agnd a vdd sclk spi programming d at a mux option pdwn dfs clk+ clk? mode controls dcs dut y cycle st abilizer sync divide 1 t o 8 oeb csb ref select adc cmos/ l vds output buffer adc cmos/ l vds output buffer AD9648 09975-001 notes 1. pin names are for the cmos pin configur a tion on l y ; see figure 7 for l vds pin names. figure 1. product highlights 1. the AD9648 1 operates from a single 1.8 v analog power supply and features a separate digital output driver supply to acco mmodate 1.8 v cmos or lvds logic families. 2. the patented sample - and - hold circuit maintains excellent performance for input frequencies up to 200 mhz and is designed for low cost, low power, and ease of use. 3. a standard serial port interface supports variou s product features and functions, such as data output formatting, internal clock divider, power - down, dco/ data timing and offset adjustments. 4. the AD9648 is packaged in a 64 - lead rohs compliant lfcsp that is pi n compatible with the ad9650 / ad9269 / ad9268 16- bit adc, the ad9258 14- bi t adc, the ad9628 / ad9231 12- bit adc s, and the ad9608/ ad9204 10- bit adc s, enabling a simple migration path between 10 - b it and 16 - bi t converters sampling from 20 msps to 125 msp s.
AD9648 rev. 0 | page 2 of 44 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? general description ......................................................................... 3 ? specifications ..................................................................................... 4 ? dc specifications ........................................................................... 4 ? ac specifications ........................................................................... 5 ? digital specifications ................................................................... 6 ? switching specifications ................................................................ 8 ? timing specifications .................................................................. 9 ? absolute maximum ratings .......................................................... 12 ? thermal characteristics ............................................................ 12 ? esd caution ................................................................................ 12 ? pin configurations and function descriptions ......................... 13 ? typical performance characteristics ........................................... 19 ? AD9648-125 ................................................................................ 20 ? AD9648-105 ................................................................................ 22 ? equivalent circuits ......................................................................... 24 ? theory of operation ...................................................................... 25 ? adc architecture ...................................................................... 25 ? analog input considerations .................................................... 25 ? voltage reference ....................................................................... 27 ? clock input considerations ...................................................... 28 ? channel/chip synchronization ................................................ 30 ? power dissipation and standby mode .................................... 30 ? digital outputs ........................................................................... 31 ? timing ......................................................................................... 31 ? built-in self-test (bist) and output test .................................. 32 ? built-in self-test (bist) ............................................................ 32 ? output test modes ..................................................................... 32 ? serial port interface (spi) .............................................................. 33 ? configuration using the spi ..................................................... 33 ? hardware interface ..................................................................... 34 ? configuration without the spi ................................................ 34 ? spi accessible features .............................................................. 34 ? memory map .................................................................................. 35 ? reading the memory map register table ............................... 35 ? memory map register table ..................................................... 36 ? memory map register descriptions ........................................ 39 ? applications information .............................................................. 41 ? design guidelines ...................................................................... 41 ? outline dimensions ....................................................................... 42 ? ordering guide .......................................................................... 42 ? revision history 7/11revision 0: initial version
AD9648 rev. 0 | page 3 of 44 general description the AD9648 is a monolithic, dual - channel, 1.8 v supply, 14- bit, 105 msps/125 msps analog - to - digital converter (adc). it features a high performance sample - and - hold circuit and on - chip voltage reference. the product uses multistage differential pipeline architecture with output error correction logic to provide 14 - bit acc uracy at 125 msps data rates and to guarantee no missing codes over the full operating temperature range. the adc contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and program mable digital test pattern generation. the available digital test patterns include built - in deterministic and pseudorandom patterns, along with custom user - defined test patterns entered via the serial port interface (spi). a differential clock input contro ls all internal conversion cycles. an optional duty cycle stabilizer (dcs) compensates for wide variations in the clock duty cycle while maintaining excellent overall adc performance. the digital output data is presented in offset binary, g ray code, or tw os complement format. a data output clock (dco) is provided for each adc channel to ensure proper latch timing with receiving logic. output logic levels of 1.8 v cmos or lvds are supported. o utput data can also be multiplexed onto a single output bus. the AD9648 is available in a 64 - lead rohs c ompliant lfcsp and is speci fied over the industrial temperature range (?40c to +85c). this product is protected by a u.s. patent.
AD9648 rev. 0 | page 4 of 44 specifications dc specifications avdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.0 v internal reference, dcs enabled, unless othe rwise noted. table 1 . AD9648 - 105 AD9648 - 125 parameter temp min typ max min typ max unit resolution full 14 14 bits accuracy no missing codes full guaranteed guaranteed offset error full ? 0.8 ? 0.3 + 0.2 ? 0.8 ? 0.3 + 0.2 % fsr gain error full ? 4.20 1.3 + 4.2 ? 5.1 1.3 + 5.1 % fsr differential nonlinearity (dnl) 1 full ? 0.5 + 1.2 ? 0.5 + 1.2 lsb 25c 0.5 0. 5 lsb integral nonlinearity (inl) 1 full ? 2.3 + 2.3 ? 2.3 + 2.3 lsb 25c 1.0 1.0 lsb matching characteristic offset error full 0.01 0.58 0.01 0.58 % fsr gain error full 0.5 4.0 0.5 4.0 % fsr temperature drift offset error full 2 2 ppm/c gain error full 50 50 ppm/c internal vol t age reference output voltage (1 v mode) full 0.9 8 1.00 1.0 2 0.9 8 1.00 1.0 2 v load regul a tion error at 1.0 ma full 2 2 mv input referred noise vref = 1.0 v 25c 0.98 0.98 lsb rms analog input in put span, vref = 1.0 v full 2 2 v p -p input capacitance 2 full 5 5 pf input resistance (differential) full 7.5 7.5 k input common - mode voltage full 0.9 0.9 v input common - mode range full 0.5 1.3 0.5 1.3 v power supplies supp ly voltage avdd full 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v supply current i avdd 1 full 81 86 9 5 100 ma i drvdd (1.8 v cmos) 1 full 19.2 22.5 ma i drvdd (1.8 v lvds) 1 full 63.5 65.0 ma
AD9648 rev. 0 | page 5 of 44 AD9648 - 105 AD9648 - 125 parameter temp min typ max min typ max unit power consumption d c input full 135. 4 155.5 mw sine wave input (drvdd = 1.8 v cmos output mode) full 1 72.3 1 81.3 202.5 211.5 mw sine wave input (drvdd = 1.8 v lvds output mode) full 180.4 189.4 211.5 220.5 mw standby power 3 full 108 120 mw power - down power fu ll 2 .0 2 .0 mw 1 measure with a low input frequency, full - scale sine wave, with approximately 5 pf loading on each output bit. 2 input capacitance refers to the effective capacitance between one differential input pin and agnd. 3 stan dby power is measured with a dc input and with the clk pins active (1.8 v cmos mode). ac specifications av dd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.0 v internal reference , dcs enabled, unless otherwise noted. table 2 . AD9648 - 105 AD9648 - 125 parameter 1 temp min typ max min typ max unit signal - to - noise - ratio (snr) f in = 9.7 mhz 25c 75.4 75.0 dbfs f in = 30.5 mhz 25c 7 5.2 7 4 . 7 dbfs f in = 70 mhz 25c 74.8 74.5 dbfs full 73.8 73.0 dbfs f in = 10 0 mhz 25c 73.8 73.9 dbfs f in = 200 mhz 25c 71.0 71.5 dbfs signal - to - noise and disto rtion (sinad) f in = 9.7 mhz 25c 74.3 73.9 dbfs f in = 30.5 mhz 25c 7 4 .0 7 3.4 dbfs f in = 70 mhz 25c 73. 4 7 3.3 dbfs full 73.0 72.8 dbfs f in = 10 0 mhz 25c 72.8 72.8 dbfs f in = 200 mhz 25c 69.6 70.3 dbfs effective nu mber of bits (enob) f in = 9.7 mhz 25c 12.0 11.9 bits f in = 30.5 mhz 25c 12.0 11.9 bits f in = 70 mhz 25c 11.8 11.8 bits f in = 10 0 mhz 25c 11.8 11. 8 bits f in = 200 mhz 25c 11.3 11.4 bits worst second or third harmonic f in = 9.7 mhz 25c ?98 ?96 dbc f in = 30.5 mhz 25c ?90 ?90 dbc f in = 70 mhz 25c ?93 ?91 dbc full ? 86 ? 82 dbc f in = 10 0 mhz 25c ?92 ?90 dbc f in = 200 mhz 25c ?81 ?84 dbc
AD9648 rev. 0 | page 6 of 44 AD9648-105 AD9648-125 parameter 1 temp min typ max min typ max unit spurious-free dynamic range (sfdr) f in = 9.7 mhz 25c 98 96 dbc f in = 30.5 mhz 25c 90 90 dbc f in = 70 mhz 25c 93 91 dbc full 86 82 dbc f in = 100 mhz 25c 92 90 dbc f in = 200 mhz 25c 81 84 dbc worst other (harmonic or spur) f in = 9.7 mhz 25c ?98 ?97 dbc f in = 30.5 mhz 25c ?96 ?97 dbc f in = 70 mhz 25c ?96 ?97 dbc full ?91 ?90 dbc f in = 100 mhz 25c ?92 ?92 dbc f in = 200 mhz 25c ?90 ?90 dbc two-tone sfdr f in = 29 mhz (?7 dbfs ), 32 mhz (?7 dbfs ) 25c 84 84 dbc crosstalk 2 full ?95 ?95 db analog input bandwidth 25c 650 650 mhz 1 see the an-835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions. 2 crosstalk is measured at 100 mhz with ?1.0 dbfs on one channel an d no input on the alternate channel. digital specifications avdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs dierential input, 1.0 v internal reference, and dcs enabled, unless otherwise noted. table 3. ad9628-105/125 parameter temp min typ max unit differential clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl internal common-mode bias full 0.9 v differential input voltage full 0.3 3.6 v p-p input voltage range full agnd - 0.3 avdd + 0.2 v input common-mode range full 0.9 1.4 v high level input current full ?10 +10 a low level input current full ?10 +10 a input capacitance full 4 pf input resistance full 8 10 12 k logic input (csb) 1 high level input voltage full 1.22 drvdd + 0.2 v low level input voltage full 0 0.6 v high level input current full ?10 +10 a low level input current full 40 132 a input resistance full 26 k input capacitance full 2 pf
AD9648 rev. 0 | page 7 of 44 ad9628-105/125 parameter temp min typ max unit logic input (sclk/dfs/sync) 2 high level input voltage full 1.22 drvdd + 0.2 v low level input voltage full 0 0.6 v high level input current (vin = 1.8 v) full ?92 ?135 a low level input current full ?10 +10 a input resistance full 26 k input capacitance full 2 pf logic input/output (sdio/dcs) 1 high level input voltage full 1.22 drvdd + 0.2 v low level input voltage full 0 0.6 v high level input current full ?10 +10 a low level input current full 38 128 a input resistance full 26 k input capacitance full 5 pf logic inputs (oeb, pdwn) 2 high level input voltage full 1.22 drvdd + 0.2 v low level input voltage full 0 0.6 v high level input current (vin = 1.8 v) full ?90 ?134 a low level input current full ?10 +10 a input resistance full 26 k input capacitance full 5 pf digital outputs cmos modedrvdd = 1.8 v high level output voltage i oh = 50 a full 1.79 v i oh = 0.5 ma full 1.75 v low level output voltage i ol = 1.6 ma full 0.2 v i ol = 50 a full 0.05 v lvds modedrvdd = 1.8 v differential output voltage (v od ), ansi mode full 290 345 400 mv output offset voltage (v os ), ansi mode full 1.15 1.25 1.35 v differential output voltage (v od ), reduced swing mode full 160 200 230 mv output offset voltage (v os ), reduced swing mode full 1.15 1.25 1.35 v 1 pull up. 2 pull down.
AD9648 rev. 0 | page 8 of 44 switching specificat ions avdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.0 v internal reference, and dcs enabled, unless otherwise noted. table 4 . AD9648 - 105 AD9648 - 125 parameter temp m in typ max min typ max unit clock input parameters input clock rate full 1000 1000 mhz conversion rate 1 dcs enabled full 20 105 20 125 msps dcs disabled full 10 105 10 125 msps clk period divide - by - 1 mode (t clk ) full 9.52 8 ns clk pulse width high (t ch ) full 4.76 4 ns aperture delay (t a ) full 1.0 1.0 ns aperture uncertainty (jitter, t j ) full 0.07 0.07 ps rms data output parameters cmos mode (drvdd = 1.8 v) data propagation delay (t pd ) full 1.8 2.9 4.4 1.8 2.9 4.4 ns dco propagation delay (t dco ) 2 full 2.0 3.1 4.4 2.0 3.1 4.4 ns dco to data skew (t skew ) full ?1.2 ?0.1 + 1.0 ?1.2 ?0.1 + 1.0 ns lvds mode (drvdd = 1.8 v) data propagation delay (t pd ) full 2.4 2.4 ns dco propagation delay (t dco ) 2 full 2 .4 2 .4 ns dco to data sk ew (t skew ) full ? 0. 20 +0.03 +0. 2 5 ? 0. 20 +0.03 +0. 2 5 ns cmos mode pipeline delay (latency) full 16 16 cycles lvds mode pip eline delay (latency) channel a/ channel b full 16/ 16 .5 16/ 16 .5 cycles wake - up time (power down) 3 full 350 350 s wake -u p time (standby) full 250 250 ns out - of - range recovery time full 2 2 cycles 1 conversion rate is the clock rate after the divider. 2 additional dco delay can be added by writing to bits[2:0] in spi register 0x17 (see table 18). 3 wake - up time is defined as the time required to return to normal operation from power - down mode.
AD9648 rev. 0 | page 9 of 44 timing specification s table 5 . parameter description limit unit sync timing requirements t ssync sync to rising edge of clk+ setup time 0. 24 ns typ t hsync sync to rising edge of clk+ hold time 0.40 ns typ spi timing requirements t ds setup time between the data and the rising edge of sclk 2 ns min t dh hold time between the data and the rising edge of sclk 2 ns min t clk period of t he sclk 40 ns min t s setup time between csb and sclk 2 ns min t h hold time between csb and sclk 2 ns min t high sclk pulse width high 10 ns min t low sclk pulse width low 10 ns min t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge 10 ns min t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge 10 ns min timing diagrams t pd t skew t ch t dco t clk n ? 16 n ? 17 n ? 1 n + 1 n + 2 n + 3 n + 5 n + 4 n n ? 15 n ? 14 n ? 13 n ? 12 vin clk+ clk? ch a/ch b d at a dcoa/dcob t a 09975-002 figure 2 . cmos default output mod e data o utput timing
AD9648 rev. 0 | page 10 of 44 t pd t skew t ch t dco t clk ch a n ? 16 ch b n ? 15 ch a n ? 14 ch b n ? 13 ch a n ? 12 ch b n ? 1 1 ch a n ? 10 ch b n ? 9 ch a n ? 8 n ? 1 n + 1 n + 2 n + 3 n + 5 n + 4 n vin clk+ clk? ch a d at a dcoa/dcob t a ch b d at a ch b n ? 16 ch a n ? 15 ch b n ? 14 ch a n ? 13 ch b n ? 12 ch a n ? 1 1 ch b n ? 10 ch a n ? 9 ch b n ? 8 09975-003 figure 3 . cmos interleaved output mode data output timing t pd t skew t ch t dco t clk ch a n ? 12 ch b n ? 12 ch a n ? 11 ch b n ? 11 ch a n ? 10 ch b n ? 10 ch a n ? 9 ch b n ? 9 ch a n ? 8 n ? 1 n + 1 n + 2 n + 3 n + 5 n + 4 n vin clk+ clk? dco+ dco? d0+ (lsb) parallel interleaved mode d0? (lsb) d13+ (msb) d13? (msb) t a ch a n ? 12 ch b n ? 12 ch a n ? 11 ch b n ? 11 ch a n ? 10 ch b n ? 10 ch a n ? 9 ch b n ? 9 ch a n ? 8 ch a0 n ? 12 ch a1 n ? 12 ch a0 n ? 1 1 ch a1 n ? 1 1 ch a0 n ? 10 ch a1 n ? 10 ch a0 n ? 9 ch a1 n ? 9 ch a0 n ? 8 d1+/0+ (lsb) channel multiplexed mode channel a d1?/d0? (lsb) d13+/d12+ (msb) d13?/d12? (msb) ch a12 n ? 12 ch a13 n ? 12 ch a12 n ? 1 1 ch a13 n ? 1 1 ch a12 n ? 10 ch a13 n ? 10 ch a12 n ? 9 ch a13 n ? 9 ch a12 n ? 8 ch b0 n ? 12 ch b1 n ? 12 ch b0 n ? 1 1 ch b1 n ? 1 1 ch b0 n ? 10 ch b1 n ? 10 ch b0 n ? 9 ch b1 n ? 9 ch b0 n ? 8 d1+/d0+ (lsb) channel multiplexed mode channel b d1?/d0? (lsb) d13+/d12+ (msb) d13?/d12? (msb) ch b12 n ? 12 ch b13 n ? 12 ch b12 n ? 1 1 ch b13 n ? 1 1 ch b12 n ? 10 ch b13 n ? 10 ch a12 n ? 9 ch a13 n ? 9 ch a12 n ? 8 09975-004 figure 4 . lvds modes for data o utput timing
AD9648 rev. 0 | page 11 of 44 sync clk+ t hsync t ssync 09975-005 figure 5 . sync input timing requirements
AD9648 rev. 0 | page 12 of 44 absol ute maximum ratings table 6 . parameter rating e lectrical 1 avdd to agnd ? 0.3 v to +2.0 v drvdd to agnd ? 0.3 v to + 2.0 v vin+a/vin+b, vin?a/vin?b to agnd ? 0.3 v to avdd + 0.2 v clk+, clk? to agnd ? 0.3 v to avdd + 0.2 v sync to agnd ? 0.3 v to avdd + 0.2 v vcm to agnd ? 0.3 v to avdd + 0.2 v rbias to agnd ? 0.3 v to avdd + 0. 2 v csb to agnd ? 0.3 v to dr vdd + 0.2 v sclk/dfs to a gnd ? 0.3 v to dr vdd + 0.2 v sdio/dcs to a gnd ? 0.3 v to drvdd + 0.2 v oeb ? 0.3 v to drvdd + 0.2 v pdwn ? 0.3 v to drvdd + 0.2 v d0a/d0b through d 13 a/d1 3 b to a gnd ? 0.3 v to drvdd + 0.2 v dcoa/dco b to a gnd ? 0.3 v to drvdd + 0.2 v e nvironmental operating temperature range (ambient) ? 40c to +85c maximum junction temperature under bias 150c storage temperature range (ambient) ? 65c to +150c 1 the inputs and outputs are rated to the supply volta ge (avdd or drvdd) + 0.2 v but should not exceed 2.1 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions a bove those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect d evice reliability. thermal characterist ics the exposed paddle must be soldered to the gro und plane for the lfcsp package. soldering the exposed paddle to the pcb increases the reliability of the solder joints and maximizes the thermal capability of the package. table 7 . thermal resistance package type airflow velocity ( m/sec) ja 1, 2 jc 1, 3 jb 1, 4 jt 1,2 unit 64- lead lfcsp 9 mm 9 mm (cp - 64- 4) 0 22.3 1.4 n/a 0.1 c/w 1.0 19.5 n/a 11.8 0.2 c/w 2.5 17.5 n/a n/a 0.2 c/w 1 per jedec 51 - 7, plus jedec 25 - 5 2s2p test board. 2 per jedec jesd51 - 2 (still air) or jedec jesd51 - 6 (moving air). 3 per mil - std 883, method 1012.1. 4 per jedec jesd51 - 8 (still air). typical ja is specified for a 4 - layer pcb with a solid ground plane. as shown table 7 , airflow improves heat dissipation, which re duces ja . in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes re duces ja . esd caution
AD9648 rev. 0 | page 13 of 44 pin configurations a nd function descript ions pin 1 indic a t or 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 d10b d1 1b dr vdd d12b d13b (msb) orb dcob dco a nc nc d0 a (lsb) dr vdd d1 a d2 a d3 a d4 a 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 a vdd a vdd vin+b vin?b a vdd a vdd rbias vcm sense vref a vdd a vdd vin? a vin+ a a vdd a vdd 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 clk+ clk? sync nc nc d0b (lsb) d1b d2b d3b dr vdd d4b d5b d6b d7b d8b d9b pdwn oeb csb sclk/dfs sdio/dcs or a d13 a (msb) d12 a d1 1a d10 a d9 a dr vdd d8 a d7 a d6 a d5 a 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AD9648 parallel cmos top view (not to scale) notes 1. nc = no connect. do not connect to this pin. 2. the exposed thermal pad on the bottom of the package provides the analog ground for the part. this exposed pad must be connected to ground for proper operation. 09975-006 figure 6. parallel cmos pin configuration (top view) table 8 . pin function descriptions (parallel cmos mode) pin no. mnemonic type description adc power supplies 10, 19, 28, 37 drvdd supply digital outp ut driver supply (1.8 v nominal ). 49, 50, 53, 54, 59, 60, 63, 64 avdd supply analog power supply (1.8 v nominal). 4, 5, 25, 26 nc no connect. do n ot c onnect to these pins . 0 agnd, exposed pad ground t he exposed thermal pad on the bottom of the package provides the analog ground for the part . this e xposed pad must be connected to ground for proper operation. adc analog 51 vin+a input differential analog input pin (+) for channel a. 52 vin ? a input differential analog input pin ( ? ) for channel a. 62 vin+b input differential analog input pin (+) for channel b. 61 vin ? b input differential analog input pin ( ? ) for channel b. 55 vref input/output voltage reference input/output. 56 sense input reference mode selection. 58 rbias input/output external reference bias resistor. 57 vcm output common - mode level bias output for analog inputs. 1 clk+ input adc clock input true. 2 clk? input adc clock input complement. digital input 3 sync input digital synchronization pin. slave mode only.
AD9648 rev. 0 | page 14 of 44 pin no. mnemonic type description digital outputs 27 d0a (lsb) output channel a cmos output data. 29 d1a output channel a cmos output data. 30 d2a output channel a cmos output data. 31 d3a output channel a cmos output data. 32 d4a output channel a cmos output data. 33 d5a output channel a cmos output data. 34 d6a output channel a cmos output dat a. 35 d7a output channel a cmos output data. 36 d8a output channel a cmos output data. 38 d9a output channel a cmos output data. 39 d10a output channel a cmos output data. 40 d11a output channel a cmos output data. 41 d12a output channel a cmos outpu t data. 42 d13a (msb) output channel a cmos output data. 43 ora output channel a overrange output . 6 d0b (lsb) output channel b cmos output data. 7 d1b output channel b cmos output data. 8 d2b output channel b cmos output data. 9 d3b output channel b cmos output data. 11 d4b output channel b cmos output data. 12 d5b output channel b cmos output data. 13 d6b output channel b cmos output data. 14 d7b output channel b cmos output data. 15 d8b output channel b cmos output data. 16 d9b output channel b cmos output data. 17 d10b output channel b cmos output data. 18 d11b output channel b cmos output data. 20 d12b output channel b cmos output data. 21 d13b (msb) output channel b cmos output data. 22 orb output channel b overrange output 24 dcoa ou tput channel a data clock output. 23 dcob output channel b data clock output. spi control 45 sclk/dfs input spi serial clock/data format select pin in external pin mode. 44 sdio/dcs input/output spi serial data i/o/duty cycle stabilizer pin in external pin mode. 46 csb input spi chip select (active low). adc configuration 47 oeb input output enable input (a ctive low). pin must be enabled via spi. 48 pdwn input power - down input in external pin mode. in spi m ode , t his input can be configured as power - down or s tandby.
AD9648 rev. 0 | page 15 of 44 pin 1 indic a t or 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 d4? d4+ dr vdd d5? d5+ d6? d6+ dco? dco+ d7? d7+ dr vdd d8? d8+ d9? d9+ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 a vdd a vdd vin+b vin?b a vdd a vdd rbias vcm sense vref a vdd a vdd vin? a vin+ a a vdd a vdd 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 clk+ clk? sync nc nc nc nc d0? (lsb) d0+ (lsb) dr vdd d1? d1+ d2? d2+ d3? d3+ pdwn oeb csb sclk/dfs sdio/dcs or+ or? d13+ (msb) d13? (msb) d12+ d12? dr vdd d1 1+ d1 1? d10+ d10 ? 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AD9648 interleaved parallel lvds top view (not to scale) notes 1. nc = no connect. do not connect to this pin. 2. the exposed thermal pad on the bottom of the package provides the analog ground for the part. this exposed pad must be connected to ground for proper operation. 09975-007 figure 7. interleaved parallel lvds pin configuration (top view) table 9 . pin function descriptions (interleaved parallel lvds mode) pin no. mnemonic type description adc power supplie s 10, 19, 28, 37 drvdd supply digital output driver supply (1.8 v nominal). 49, 50, 53, 54, 59, 60, 63, 64 avdd supply analog power supply (1.8 v nominal). 4, 5, 6, 7 nc no connect. do not c onnect to these pins . 0 agnd, exposed pad ground the exposed thermal pad on the bottom of the package provides the analog ground for the part. this exposed pad must be connected to ground for proper operation. adc analog 51 vin+a input differential analog input pin (+) for channel a. 52 vin ? a input differential analog input pin ( ? ) for channel a. 62 vin+b input differential analog input pin (+) for channel b. 61 vin ? b input differential analog input pin ( ? ) for channel b. 55 vref input/output voltage reference input/output. 56 sense inpu t reference m ode s election. 58 rbias input/output external reference bias resistor. 57 vcm output common - mode level bias output for analog inputs. 1 clk+ input adc clock input true. 2 clk? input adc clock input complement. digital input 3 sync input digital synchronization pin. slave mode only. digital outputs 9 d0+ (lsb) output channel a/channel b lvds output data 0 true. 8 d0? (lsb) output channel a/channel b lvds output data 0 complement. 12 d1+ output channel a/channel b lvds output data 1 tru e. 11 d1? output channel a/channel b lvds output data 1 complement.
AD9648 rev. 0 | page 16 of 44 pin no. mnemonic type description 14 d2+ output channel a/channel b lvds output data 2 true. 13 d2? output channel a/channel b lvds output data 2 complement. 16 d3+ output channel a/channel b lvds output data 3 true. 15 d3? output channel a/channel b lvds output data 3 complement. 18 d4+ output channel a/channel b lvds output data 4 true. 17 d4? output channel a/channel b lvds output data 4 complement. 21 d5+ output channel a/channel b lvds output data 5 true. 20 d5? output channel a/channel b lvds output data 5 complement. 23 d6+ output channel a/channel b lvds output data 6 true. 22 d6? output channel a/channel b lvds output data 6 complement. 27 d7+ output channel a/channel b lvds output data 7 true. 26 d7? output channel a/channel b lvds output data 7 complement. 30 d8+ output channel a/channel b lvds output data 8 true. 29 d8? output channel a/channel b lvds output data 8 complement. 32 d9+ output channel a/channel b lvds output data 9 true. 31 d9? outp ut channel a/channel b lvds output data 9 complement. 34 d10+ output channel a/channel b lvds output data 10 true. 33 d10? output channel a/channel b lvds output data 10 complement. 36 d11+ output channel a/channel b lvds output data 11 true. 35 d11? output channel a/channel b lvds output data 11 complement. 39 d12+ output channel a/channel b lvds output data 12 true. 38 d12? output channel a/channel b lvds output data 12 complement. 41 d13+ (msb) output channel a/channel b lvds output data 13 true. 40 d13? (msb) output channel a/channel b lvds output data 13 complement. 43 or+ output channel a/channel b lvds overrange output true. 42 or ? output channel a/channel b lvds overrange output complement. 25 dco+ output channel a/channel b lvds data clo ck output true. 24 dco? output channel a/channel b lvds data clock output complement. spi control 45 sclk/dfs input spi serial clock/data format select pin in external pin mode. 44 sdio/dcs input/output spi serial data i/o/duty cycle stabilizer pin in external pin mode. 46 csb input spi chip select (active low). adc configuration 47 oeb input output enable input (active low). pin must be enabled via spi. 48 pdwn input power - down input in external pin mode. in spi m ode , t his input can be configured a s p ower - down or s tandby.
AD9648 rev. 0 | page 17 of 44 pin 1 indic a t or 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 b d9?/d8? b d9+/d8+ dr vdd b d 1 1?/d10? b d 1 1+/d10+ b d13?/d12? (msb) b d13+/d12+ (msb) dco? dco+ a d1?/d0? (lsb) a d1+/d0+ (lsb) dr vdd a d3?/d2? a d3+/d2+ a d5?/d4? a d5+/d4+ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 a vdd a vdd vin+b vin?b a vdd a vdd rbias vcm sense vref a vdd a vdd vin? a vin+ a a vdd a vdd 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 clk+ clk? sync nc nc nc nc b d1?/d0? (lsb) b d1+/d0+ (lsb) dr vdd b d3?/d2? b d3+/d2+ b d5?/d4? b d5+/d4+ b d7?/d6? b d7+/d6+ pdwn oeb csb sclk/dfs sdio/dcs or+ or? a d13+/d12+ (msb) a d13?/d12? (msb) a d 1 1+/d10+ a d 1 1?/d10? dr vdd a d9+/d8+ a d9?/d8? a d7+/d6+ a d7?/d6? 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AD9648 channe l mu l tiplexed l vds top view (not to scale) notes 1. nc = no connect. do not connect to this pin. 2. the exposed thermal pad on the bottom of the package provides the analog ground for the part. this exposed pad must be connected to ground for proper operation. 09975-008 figure 8 . channel multiplexed lvds pin configuration (top view) table 10 pin function descriptions (channel multiplexed parallel lvds mode) pin no. mnemonic type description adc power supplies 10, 19, 28, 37 drvdd supply digital output driver supply (1.8 v nominal). 49, 50, 53, 54, 59, 60, 63, 64 avdd supply analog power supply (1.8 v nominal). 4, 5, 6, 7 nc do not connect. 0 agnd, exposed pad ground the exposed thermal p ad on the bottom of the package provides the analog ground for the part. this exposed pad must be connected to ground for proper operation. adc analog 51 vin+a input differential analog input pin (+) for channel a. 52 vin ? a input differential analog input pin ( ? ) for channel a. 62 vin+b input differential analog input pin (+) for channel b. 61 vin ? b input differential analog input pin ( ? ) for channel b. 55 vref input/output voltage reference input/output. 56 sense inpu t reference mode selection. 58 rbias input/output external reference bias resistor. 57 vcm output common - mode level bias output for analog inputs. 1 clk+ input adc clock input true. 2 clk? input adc clock input complement. digital input 3 sync input digital synchronization pin. slave mode only.
AD9648 rev. 0 | page 18 of 44 pin no. mnemonic type description digital outputs 8 b d1? /d0? (lsb) output channel b lvds output data 1/ data 0 complement. 9 b d1+/ d0+ (lsb) output channel b lvds output data 1/ data 0 true. 11 b d3?/ d2? output channel b lvds output data 3 / d ata 2 complement. 12 b d3+/ d2+ output channel b lvds output data 3/ data 2 true. 13 b d5?/ d4? output channel b lvds output data 5/ data 4 complement. 14 b d5+/ d4+ output channel b lvds output data 5/ data 4 true. 15 b d7?/ d6? output channel b lvds o utput data 7/ data 6 complement. 16 b d7+/ d6+ output channel b lvds output data 7/ data 6 true. 17 b d9?/ d8? output channel b lvds output data 9/ data 8 complement. 18 b d9+/ d8+ output channel b lvds output data 9/data 8 true. 20 b d11?/ d10? output ch annel b lv ds output data 11/ data 10 complement. 21 b d11+/ d10+ output channel b lvds output data 11/ data 10 true. 22 b d13?/d12? (msb) output channel b lvds output data 13/ data 12 complement. 23 b d13+/ d12+ (msb) output channel b lvds output data 13/data 12 true. 26 a d1?/ d0? (lsb) output channel a lvds output data 1/ data 0 complement. 27 a d1+ /d0+ (lsb) output channel a lvds output data 1/ data 0 true. 29 a d3?/ d2? output channel a lvds output data 3/ data 2 complement. 30 a d3+/ d2+ output chan nel a lvds output data 3/ data 2 true. 32 a d5+ / d4+ output channel a lvds output data 5/ data 4 complement. 31 a d5 ? / d4 ? output channel a lvds output data 5/ data 4 true. 34 a d7 + / d6 + output channel a lvds output data 7/ data 6 complement. 33 a d7 ? / d6 ? output channel a lvd s output data 7/ data 6 true. 36 a d9 + / d8 + output channel a lvds output data 9/ data 8 complement. 35 a d9 ? / d8 ? output channel a lvds output data 9/ data 8 true. 39 a d11 + / d10 + output channel a lvds output data 11/data 10 complement. 38 a d11 ? / d10 ? output channel a lvds output data 11/ data 10 true. 41 a d13 + / d12 + (msb) output channel a lvds output data 13/ data 12 complement. 40 a d13 ? / d12 ? (msb) output channel a lvds output data 13/ data 12 true. 43 or+ output channel a/channel b lvds overrange output tr ue. 42 or? output channel a/channel b lvds overrange output complement. 25 dco+ output channel a/channel b lvds data clock output true. 24 dco? output channel a/channel b lvds data clock output complement. spi control 45 sclk/dfs input spi serial cloc k/data format select pin in external pin mode. 44 sdio/dcs input/output spi serial data i/o/duty cycle stabilizer pin in external pin mode. 46 csb input spi chip select (active low). adc configuration 47 oeb input output enable input (active low). pin must be enabled via spi. 48 pdwn input power - down input in external pin mode. in spi mode, this input can be configured as power - down or standby.
AD9648 rev. 0 | page 19 of 44 typical performance characteristics AD9648 - 125 avdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ? 1.0 dbfs differential input, 1.0 v internal reference, and dcs enabled, unless otherwise noted. ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 60 50 amplitude (dbfs) frequenc y (mhz) 125msps 9.7mhz at ?1dbfs snr = 74.4db (75.4dbfs) sfdr = 95.4dbc 09975-014 figure 9. single - tone fft with f in = 9.7 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 60 amplitude (dbfs) frequenc y (mhz) 125msps 30.5mhz at ?1dbfs snr = 74.0db (75.0dbfs) sfdr = 86.0dbc 09975-022 figure 10 . single - tone fft with f in = 30.5 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 60 amplitude (dbfs) frequenc y (mhz) 125msps 70.1mhz at ?1dbfs snr = 73.8db (74.8dbfs) sfdr = 95.8dbc 09975-023 figur e 11 . single - tone fft with f in = 70.1 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 60 amplitude (dbfs) frequenc y (mhz) 125msps 100.5mhz at ?1dbfs snr = 73.3db (74.3dbfs) sfdr = 92.3dbc 09975-024 figure 12 . single - tone fft with f in = 100 .5 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 60 amplitude (dbfs) frequenc y (mhz) 125msps 200.5mhz at ?1dbfs snr = 70.9db (71.9dbfs) sfdr = 83.6dbc 09975-025 figure 13 . single - tone fft with f in = 200 .5 mhz
AD9648 rev. 0 | page 20 of 44 AD9648 - 125 avdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.0 v internal reference, and dcs enabled, unless otherwise noted . 6m 0 ?15 ?30 ?45 ?60 ?75 ?90 ?105 ?120 ?135 12m 18m 24m 30m 36m 42m 48m 54m 60m 6m 0 ?15 ?30 ?45 ?60 ?75 ?90 ?105 ?120 ?135 12m 18m 24m 30m 36m 42m 48m 54m 60m 2f 1 ? f 2 2f 2 ? f 1 2 f 1 + f 2 frequenc y (mhz) amplitude (hz) 09975-067 figure 14 . two - tone fft with f in1 = 2 9 mhz and f in2 = 3 2 mhz 50 55 60 65 70 75 80 85 90 95 100 0 50 100 150 200 250 analog input frequenc y (mhz) snr/sfdr (dbfs/dbc) sf d r ( d bc ) s n r ( d bfs ) 09975-069 figure 15 . snr/sfdr vs. input frequency (ain) with 2 v p - p full scale 0 20 40 60 80 100 120 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 snr/sfdr (dbfs) input amplitude (dbfs) 09975-068 sfdrfs snr sfdr snrfs figure 16 . snr/sfdr vs. input amplitude (ain) with f in = 9.7 mhz ?1 10 ?90 ?70 ?50 ?30 ?10 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 sfdr/imd3 (dbc/dbfs) input amplitude (dbfs) sf d r ( d bc ) i m d3 ( d bc ) sf d r ( d bfs ) i m d3 ( d bfs ) 09975-065 figure 17 . two - tone sfdr/imd3 vs. input amplitude (ain) with f in1 = 29 mhz and f in2 = 32 mhz 0 20 40 60 80 100 120 5 15 25 35 45 55 65 75 85 95 105 1 15 125 snr/sfdr (dbfs/dbc) sample r a te (msps) snr (dbfs) sfdr (dbc) 09975-020 figure 18 . snr/sfdr vs. sample rate with ain = 9.7 mhz 0 20 40 60 80 100 120 snr/sfdr (dbfs/dbc) 5 15 25 35 45 55 65 75 85 95 105 1 15 125 sample r a te (msps) snr (dbfs) sfdr (dbc) 09975-021 figure 19 . snr/sfdr vs. sample rate with ain = 70.1 mhz
AD9648 rev. 0 | page 21 of 44 0 2000 4000 6000 8000 10000 12000 14000 16000 output code ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1 1.5 2 dn l error (lsb) 09975-019 figure 20 . dnl error with f in = 9. 7 mhz 0 50,000 100,000 150,000 200,000 250,000 300,000 350,000 400,000 450,000 n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 number of hits output code 09975-074 figure 21 . short ed input histogram ?2.0 ?1.5 ?1.0 -0.5 0 0.5 1.0 1.5 2.0 0 2000 4000 6000 8000 10000 12000 14000 16000 in l error (lsb) output code 09975-018 figure 22 . inl error with f in = 9.7 mhz
AD9648 rev. 0 | page 22 of 44 AD9648 - 105 avdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.0 v internal r eference, and dcs enabled, unless otherwise noted. ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 amplitude (dbfs) frequenc y (mhz) 105msps 9.7mhz at ?1dbfs snr = 74.7db (75.7dbfs) sfdr = 98.7dbc 09975-014 figure 23 . single - tone fft with f in = 9.7 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 amplitude (dbfs) frequenc y (mhz) 105msps 30.5mhz at ?1dbfs snr = 74.5db (75.5dbfs) sfdr = 89.9dbc 09975-015 figure 24 . single - tone fft with f in = 30.5 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 amplitude (dbfs) frequenc y (mhz) 105msps 70.1mhz at ?1dbfs snr = 73.9db (74.9dbfs) sfdr = 94.9dbc 09975-013 figure 25 . single - tone ff t with f in = 70. 1 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) frequenc y (mhz) 0 10 20 30 40 50 09975-016 105msps 100.5mhz at ?1dbfs snr = 73.4db (74.4dbfs) sfdr = 94.9dbc figure 26 . single - tone fft with f in = 100 .5 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 amplitude (dbfs) frequenc y (mhz) 09975-017 105msps 200.5mhz at ?1dbfs snr = 69.5db (70.5dbfs) sfdr = 82.6dbc figure 27 . single - tone fft with f in = 200.5 mhz
AD9648 rev. 0 | page 23 of 44 50 55 60 65 70 75 80 85 90 95 100 0 50 100 150 200 250 snr/sfdr (dbfs/dbc) analog input frequenc y (mhz) sf d r ( d bc ) s n r ( d bfs ) 09975-075 figure 28 . snr/sfdr vs. input frequency (ain) wi th 2 v p - p full scale 0 20 40 60 80 100 120 5 15 25 35 45 55 65 75 85 95 105 snr/sfdr (dbfs/dbc) sample r a te (msps) sfdr (dbc) snr (dbfs) 09975-012 figure 29 . snr/sfdr vs. sample rate with ain = 9.7 mhz ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 2000 4000 6000 8000 10000 12000 14000 16000 dn l error (lsb) output code 09975-010 figure 30 . dnl error with f in = 9.7 mhz 0 20 40 60 80 100 120 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 snr/sfdr (dbfs/dbc) input amplitude (dbfs) sf d rf s s n rf s sf d r s n r 09975-077 figure 31 . snr/sfdr vs. input amplitude (ain) with f in = 9.7 mhz 0 20 40 60 80 100 120 5 15 25 35 45 55 65 75 85 95 105 snr/sfdr (dbfs/dbc) sample r a te (msps) sfdr (dbc) snr (dbfs) 09975-0 1 1 figure 32 . snr/sfdr vs. sample rate with ain = 70.1 mhz ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 2000 4000 6000 8000 10000 12000 14000 16000 in l error (lsb) output code 09975-009 figure 33 . inl error with f in = 9.7 mhz
AD9648 rev. 0 | page 24 of 44 equivalent circuits a vdd vinx 09975-039 figure 34 . equivalent analog input ci rcuit clk+ clk? 0.9v 15k? 5? 5? 15k? 09975-040 figure 35 . equivalent clock input circuit drvdd pad 09975-047 figure 36 . equivalent digital output circuit 30k? 30k? sdio/dcs 350? a vdd dr vdd 09975-042 figure 37 . equivalent sdio/dcs input circuit 350? dr vdd 30k? sclk/dfs, sync, oeb, and pdwn 09975-045 figure 38 . equivalent sclk/dfs, sync, oeb , and pdwn input circuit sense 375? a vdd 09975-043 figure 39 . equivalent sense circuit 30k? csb 350? a vdd dr vdd 09975-044 figure 40 . equivalent csb input circuit 7 . 5k ? v r ef 375 ? a v d d 09975-048 figure 41 . equivalent vref c ircuit
AD9648 rev. 0 | page 25 of 44 theory of operation the AD9648 dual adc design can be used for diversity reception of signals, where the adcs are operating identically on the same carrier but from two separate antennae. the adcs can also be operated with independent analog inputs. the user can sample any f s /2 frequency segment from dc to 200 mhz, using appropriate low - pass or band - pass filtering at the adc inputs with little loss in adc performance. operation to 300 mhz analog input is permitted but occurs at the expense of increased adc noise and distortion. in nondiversity applications, the AD9648 can be used as a base - band or direct downconversion receiver, where one adc is used for i input data and the other is used for q input data. synchronization capability is provided to allow synchronized timing between multiple channels or multiple devices. programming and control of the AD9648 is a ccomplished using a 3 - bit spi - compatible serial interface. adc architecture the AD9648 architecture consists of a multistage, pipelined adc . each stage provides sufficient overlap to correct for flash errors in the preceding stage. the quantized outputs from each stage are combined into a final 14 - bit result in the digital correction logic. the pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate wi th preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched - capacitor dac and an interstage residue amplifier (for example, a multipl ying digital - to - analog converter (mdac)). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correcti on of flash errors. the last stage simply consists of a flash adc. the output staging block aligns the data, corrects errors, and passes the data to the cmos/lvds output buffers. the output buffers are powered from a separate (drvdd) supply, allowing digit al output noise to be separated from the analog core. during power - down, the output buffers go into a high impedance state. analog input conside rations the analog input to the AD9648 is a differential switched - capacitor circuit designed for processing differential input signals. this circuit can support a wide common - mode range while maintaining excellent performance. by using an input common - mode voltage of midsupply, users can minimize signal - dependent e r rors and achieve optimum performance. s s c p a r c s a m p l e c s a m p l e c p a r v i n ? x h s s h h v i n +x h 09975-049 figure 42 . switched - capacitor input circuit the clock signal alternately switches the input circuit between sa m ple - and - hold mode (see figure 42 ). w hen the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within one - half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current injec ted from the output stage of the driving source. in addition, low q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and, therefore, achieve the maximum bandwidth of the adc. suc h use of low q inductors or ferrite beads is required when driving the converter front end at high if frequencies. either a shunt capacitor or two single - ended capacitors can be placed on the inputs to provide a matching passive network. this ultimately cr eates a low - pass filter at the i n put to limit unwanted broadband noise. see the an - 742 application note, the an - 827 application note , and the analog dialogue articl e transformer - coupled front - end for wideband a/d converters (volume 39, april 2005) for more information . in general, the precise values depend on the appl i cati on.
AD9648 rev. 0 | page 26 of 44 input common mode the analog inputs of the AD9648 are not internally dc - biased. therefore, in ac - coupled applications, the user must provide a dc bias exte r nally. setting the device so that vcm = av dd /2 i s recommended for optimum performance, but the device can function over a wider range with reaso n able performance, as shown in figure 43. an on - board, common - mode voltage reference is included in the design and is available from the vcm pin. the vcm pin must be decoupled to ground by a 0.1 f capacitor, as described in the applications information section. 0 10 20 30 40 50 60 70 80 90 100 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 snr/sfdr (dbfs/dbc) input common-mode vo lt age (v) sf d r ( d bc ) s n r ( d bfs ) 09975-072 figure 43 . snr/sfdr vs. input common - mode voltage, f in = 70 mhz, f s = 125 msps differential input configurations optimum performance is achieved while driving the AD9648 in a differential input configuration. for baseband applications, the ad8138 , ada4937 - 2 , and ada4938 - 2 differential drivers provide excellent performance and a flexible interface to the adc. the output co m mon - mode voltage of the ada4938 - 2 is easily set with the vcm pin of the AD9648 (see figure 44 ), and the driver can be configured in a sallen - key filter topology to provide band limi t ing of the input signal. a v d d v i n 76 . 8 ? 120 ? 0 . 1 f 33 ? 33 ? 10 p f 200 ? 200 ? 90 ? ada 493 8 ad c v i n ? x v i n +x v c m 09975-050 figure 44 . differential input configuration using the ada4938 - 2 for baseband applications below ~10 mhz where snr is a key para meter, differential transformer - coupling is t he reco mmended input config u ration. an example is shown in figure 45 . to bias the analog input, the vcm voltage can be connected to the center tap of the seco n dary winding of the transformer. 2 v p -p 49 . 9 ? 0 . 1 f r r c ad c v c m v i n +x v i n ? x 09975-051 figure 45 . differential transformer - coupled configuration the signal characteristics must be considered when selecting a transformer. most rf transformers saturate at frequencies b e low a few megahertz (mhz). excessive signal power can also cause core saturation, which leads to distortion. at input frequencies in the second nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true snr performance of the AD9648 . for applications above ~10 mhz where snr is a key parameter, differential double balun coupling is the recommended input config u ration (see figure 46). an alternative to using a transformer - coupled input at fr equencies in the second nyquist zone is to use the ad8352 differe n tial driver. an example is shown in figure 47 . see the ad8352 data sheet for more information. ad c r 0 . 1 f 0 . 1 f 2 v p -p v c m c r 0 . 1 f s 0 . 1 f 25 ? 25 ? s p a p v i n +x v i n ? x 09975-053 figure 46 . differential double balun input configuration ad 835 2 0 ? 0 ? c d r d r g 0 . 1 f 0 . 1 f 0 . 1 f 0 . 1 f 1 6 1 2 3 4 5 1 1 0 . 1 f 0 . 1 f 1 0 1 4 0 . 1 f 8 , 1 3 v c c 200 ? 200 ? ana l og i n p u t ana l og i n p u t r r c ad c v c m v i n +x v i n ? x 09975-054 figure 47 . differential input configuration using the ad8352
AD9648 rev. 0 | page 27 of 44 in any configuration, the value of shunt capacitor c is dependent on the input frequency and source impedance and may need to be reduced or removed. table 11 displays the suggested values to set the rc network. however, these values are dependent on t he input signal and should be used only as a star t ing guide. table 11 . example rc network frequency range (mhz) r series (? each) c differential (pf) 0 to 70 33 22 70 to 200 125 open single - ended input configuration a single - ended input can provide adequate performance in cost - sensitive applications. in this configuration, sfdr and distortion performance degrad e due to the large input common - mode swing. if the source i m pedances on each input are matched, there should be little effect on snr performance. figu re 48 shows a typical single - ended input configuration. 1 v p - p r r c 49 . 9 ? 0 . 1 f 10 f 10 f 0 . 1 f a v d d 1k ? 1 k ? 1 k ? 1 k ? a d c a v d d v i n +x v i n ? x 09975-052 figu re 48 . single - ended input configuration voltage reference a stable and accurate 1.0 v voltage reference is built into the AD9648 . the vref can be configured using either the internal 1. 0 v reference or an externally applied 1.0 v reference voltage. the various re f erence modes are summarized in the sections that follow. the reference decoupling section describes the best practices pcb layout o f the reference. internal reference connection a comparator within the AD9648 detects the potential at the sense pin and configures the reference into two possible modes, which are summarized in table 12 . if sense is grounded, the reference amplifier switch is connected to the internal resistor divider (see figure 49 ), setting vref to 1.0 v. v r ef se n se 0 . 5 v ad c se l e c t l ogi c 0 . 1 f 1 . 0 f v i n ? a / v i n ? b v i n + a / v i n +b ad c c o r e 09975-055 figure 49 . internal reference configuration if the internal reference of the AD9648 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be co nsidered. figure 50 shows how the internal reference voltage is affected by loa d ing. 0 ?3 . 0 0 2 . 0 l o ad curr e n t ( ma ) r e f e r e nc e v o lt a g e e rr o r ( % ) ?0 . 5 ?1 . 0 ?1 . 5 ?2 . 0 ?2 . 5 0 . 2 0 . 4 0 . 6 0 . 8 1 . 0 1 . 4 1 . 6 1 . 8 1 . 2 i n t e rna l v r e f = 1.00v 09975-078 figure 50 . v ref accuracy vs. load current table 12 . reference configurat ion summary selected mode sense vol t age (v) resulting vref (v) resulting differe n tial span (v p - p) fixed internal refe r ence agnd to 0.2 1.0 internal 2.0 fixed external re f erence avdd 1.0 applied to external vref pin 2.0
AD9648 rev. 0 | page 28 of 44 external reference operation t he use of an external reference may be necessary to enhance the gain accuracy of the adc or improve thermal drift charac - teristics. figure 51 shows the typical drift characteri s tics of the internal reference in 1 .0 v mode. 4 3 2 1 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ?4 0 ?2 0 0 2 0 4 0 6 0 8 0 t empe ra t ur e ( c ) v r e f e rr o r ( m v) v r e f e rr o r ( m v) 09975-079 figure 51 . typical v ref drift when the sense pin is tied to avdd, the internal reference is disabled, allowing the use of an external reference. an internal reference buffer loads the external reference with an equival ent 7.5 k? load (see figure 41 ). the internal buffer generates the positive and negative full - scale references for the adc core. therefore, the external reference must be limited to a maximum of 1.0 v. clock input considerations for optimum performance, clock the AD9648 sample clock inputs, clk+ and clk?, with a differential signal. the signal is typically ac - coupled into the clk+ and clk? pins via a transformer or capa citors. these pins are biased internally (see figure 52 ) and require no exte r nal bias. 0 . 9 v a v d d 2 p f 2 p f c l k ? c l k + 09975-058 figure 52 . equivalent clock input circuit clock input options th e AD9648 has a very flexible clock input structure. the clock in put can be a cmos, lvds, lvpecl, or sine wave signal. regardless of the type of signal being used, clock source jitter is of the most concern, as described in the jitter considerations section. figure 53 and figure 54 show two preferred methods for clock - ing the AD9648 (at clock rates up to 1 ghz prior to internal clk divider). a low jitter cloc k source is converted from a single - ended signal to a di f ferential signal using either an rf transformer or an rf balun. the rf balun configuration is recommended for clock frequencies between 125 mhz and 1 ghz, and the rf transformer is recom - mended for clock frequencies from 10 mhz to 200 mhz. the back - to - back schottky diodes across the transformer/balun secondary limit clock excursions into the AD9648 to approximately 0.8 v p - p differe n tial. this limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9648 while preserving the fast rise and fall times of the signal that are critical to a low jitter performance. 0 . 1 f 0 . 1 f 0 . 1 f 0 . 1 f s ch o tt k y d io d es: h sms 282 2 c l o c k i n p u t 50 ? 100 ? c l k ? c l k + ad c m i n i - c i rc u i ts ? ad t 1 - 1 wt , 1 : 1 z x f mr 09975-059 figure 53 . transformer - coupled differential clock (up to 200 mhz) 0 . 1 f 0 . 1 f 1 n f c l o c k i n p u t 1 n f 50 ? c l k ? c l k + s ch o tt k y d io d es: h sms 282 2 ad c 09975-060 figure 54 . balun - coupled differential clock (up to 1 g hz)
AD9648 rev. 0 | page 29 of 44 if a low jitter clock source is not available, another option is to ac couple a differential pecl signal to the sample clock input pins, as shown in figure 55 . the ad9510/ ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 / ad9517 clock drivers offer excellent jitter perfor m ance. 1 0 0 ? 0 . 1 f 0 . 1 f 0 . 1 f 0 . 1 f 240 ? 240 ? 50k ? 50k ? c l k ? c l k + c l o c k i n p u t c l o c k i n p u t ad c ad 951 x pe c l dr i ver 09975-061 figure 55 . differentia l pecl sample clock (up to 1 g hz) a third option is to ac couple a differential lvds signal to the sa m ple clock input pins, as shown in figure 56 . the ad9510/ ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 / ad9517 clock drivers offer excellent jitter perfor m ance. 1 0 0 ? 0 . 1 f 0 . 1 f 0 . 1 f 0 . 1 f 50k ? 50k ? c l k ? c l k + ad c c l o c k i n p u t c l o c k i n p u t ad 951 x l v d s dr i ver 09975-062 figure 56 . differentia l lvds sample clock (up to 1 g hz) in some applications, it may be ac ceptable to drive the sample clock inputs with a single - ended 1.8 v cmos signal. in such applica tions, drive the clk+ pin directly from a cmos gate, and bypass the clk? pin to ground with a 0.1 f c a pacitor (see figure 5 7 ). o p tio na l 100 ? 0 . 1 f 0 . 1 f 0 . 1 f 50 ? 1 1 50 ? r es i s t o r i s o p t io na l . c l k ? c l k + ad c v c c 1k ? 1k ? c l o c k i n p u t ad 951 x c m o s dr i ver 09975-063 figure 57 . single - ended 1.8 v cmos input clock (up to 200 mhz) input clock divider the AD9648 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. the AD9648 clock divider can be synchronized using the external sync input. bit 1 and bit 2 of register 0x 3a allow the clock divider to be resynchronized on every sync signa l or only on the first sync signal after the register is written. a valid sync causes the clock divider to reset to its initial state. this synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input s ampling . clock duty cycle typical high speed adcs use both clock edges to generate a variety of internal timing signals and, as a result, may be sens i tive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dyna mic performance characteristics. the AD9648 contains a duty cycle stab i lizer (dcs) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. this allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9648 . noise and distortion perform - ance are nearly flat for a wide range of duty c y cles with the dcs on, as sh own in figure 58. jitter in the rising edge of the input is still of concern and is not easily reduced by the internal stabilization circuit. the duty cycle control loop does not function for clock rates less t han 20 mhz, nominally. the loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease be fore the dcs loop is relocked to the input signal. 09975-076 40 45 50 55 60 65 70 75 80 35 40 45 50 55 60 65 snr (dbfs) positive duty cycle (%) snr (dcs off) snr (dcs on) figure 58 . snr vs. dcs on/off
AD9648 rev. 0 | page 30 of 44 jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr from the low fre - quency snr (snr lf ) at a given input frequency ( f input ) due to jitter ( t jrms ) can be calc u lated by snr hf = ?10 log[(2 f input t jrms ) 2 + 10 ) 10 / ( lf snr ? ] in the previous equation, the rms aperture jitter represents the clock input jitter specification. if undersampling applications are particularly sensitive to jitter, as illustrated in figure 59. 8 0 7 5 7 0 6 5 6 0 5 5 5 0 4 5 1 1 0 10 0 1 k f r e q u e nc y (m h z) s nr ( d b f s) 0 . 5 p s 0 . 2 p s 0 . 05 p s 1 . 0 p s 1 . 5 p s 2 . 0 p s 2 . 5 p s 3 . 0 p s 09975-080 figure 59 . snr vs. input frequency and jitter the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9648 . to avoid modulating the clock signal with digital noise, keep p ower supplies for clock drivers separate from the adc output driver supplies . low jitter, crystal - controlled oscillators make the best clock sources. i f the clock is generated from another type of source (by gating, dividing, or another met h od), it should be retimed by the original clock at the last step. see the an - 501 application note and the an - 756 application note , available on www.analog.com for more information. channel/chip synchro niation the AD9648 has a sync input that of fers the user flexible synchronization options for synchronizing sample clocks across multiple adcs . the input clock divider can be enabled to synchronize on a single occurrence of the sync signal or on every occurrence. the sync input is internally sync hronized to the sample clock; however, to ensure there is no timing uncertainty between multiple parts, the sync input signal should be externally synchronized to the input clock signal, meeting the setup and hold times shown in table 5 . drive the sync input using a single - ended cmos - type signal. power dissipation an d standby mode as shown in figure 60 , the analog core power dissipated by the AD9648 is proportional to its sample rate. the digital power dissipation of the cmos outputs are determined primarily by the strength of the digital drivers and the load on each output bit. the maximum drvdd current (idrvdd) can be calculated a s i drvdd = v drvdd c load f clk n where n is th e number of output bits (30 , in the case of the AD9648 ). this maximum current occurs when every output bit switches on every clock cycle, that is, a full - scale square wave at the nyquist frequency of f clk /2. in practice, the drvdd current is estab - lished by the average number of output bits switching, which is determined by the sample rate and the characte r istics of the analog input signal. redu cing the capacitive load presented to the output drivers can minimize digital power co n sumption. the data in figure 60 was taken in cmos mode using the same operating conditions as those used for the power suppli es and power consumption specifications in table 1 , with a 5 pf load on each ou t put driver. 40 60 80 100 120 140 160 180 200 220 0 10 20 30 40 50 60 70 80 90 100 5 25 45 65 85 105 125 power (mw) supp l y current (a) encode r a te (msps) i avdd t ot a l p ow er i drvdd 09975-070 figure 60 . AD9648 - 125 power and current vs. clock rate (1.8 v cmos output mode) 40 60 80 100 120 140 160 180 200 0 10 20 30 40 50 60 70 80 90 5 25 45 65 85 105 power (mw) supp l y current (a) encode r a te (msps) i avdd i drvdd to t a l p o w e r 09975-066 figure 61 . AD9648 - 105 power and current vs. clock rate (1.8 v cmos output mode)
AD9648 rev. 0 | page 31 of 44 the AD9648 is placed in power - down mode either by the spi port or by asserting the pdwn pin high. in this state, t he adc typically dissipates less than 2 mw . during power - down, the output drivers are placed in a high impedance state. asserting the pdwn pin low returns the AD9648 to its normal operating mode. note that pdwn is re f erenced to the digital output driver supply (drvdd) and should not exceed that supply voltage. low power dissipation in power - down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. internal capacitors ar e discharged when entering power - down mode and then must be recharged when r e turning to normal operation. as a result, wake - up time is related to the time spent in power - down mode, and shorter power - down cycles result in proportio n ally shorter wake - up time s. when using the spi port interface, the user can place the adc in power - down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake - up times are required. see the memory map section for more details. digital outputs the AD9648 output drivers can be configured to interface with either 1.8 v cmos or 1.8 v lvds logic families. the default output mode is cmos, with each channel output on separate busses as shown in figure 2 . in cmos output mode, the cmos output drivers are sized to provide sufficient output current to drive a wide variety of logic families. however, larg e drive currents tend to cause current glitches on the supplies and may affect converter performance. applications requiring the adc to drive large capacitive loads or large fanouts may require external buffers or latches. the cmos o utput can also be con figured for interleaved cmos output mode via the spi port. in interleaved cmos mode, the data for both channels is output onto a single output bus to reduce the total number of traces required. the timing diagram for interleaved cmos output mode is shown i n figure 3 . the interleaved cmos output mode is enabled globally onto both output channels via bit 5 in register 0x14. the unused channel output can be disabled by selecting the appropriate device index (bit 1 or b it 0) in register 0x05, then writing a 1 to local (channel specific) output port d isable bit in register 0x14. the output data format can be selected to be either offset binary or twos complement by setting the sclk/dfs pin when opera t ing in the external p in mode (see table 13 ). as detailed in the an - 877 application note, interfacing to high speed adcs via spi , the data format can be selected for offset binar y, twos c omplement, or gray code when using the spi co n trol. table 13 . sclk/dfs mode selection (external pin mode) voltage at pin sclk/dfs sdio/dcs agnd offset binary (default) dcs disabled drvdd twos complement dcs enabled (default) digi tal output enable function (oeb) the AD9648 has a flexible three - state ability for the digital output pins. the three - state mode is enabled through the spi interface and can subsequently be controlled using the oeb pin or through the spi. once enabled via spi (bit 7) in register 0x101 , and the oeb pin is low, the output data drivers and dcos are enabled. if the oeb pin is high, the ou t put data drivers and dcos are placed in a high impedance state. this oeb funct ion is not intended for rapid access to the data bus. note that oeb is re f erenced to the digital output driver supply (drvdd) and should not exceed that supply voltage. when using the spi interface, the data outputs and dco of each channel can be independe ntly three - stated by using the output disable bit (bit 4) in register 0x14. timing the AD9648 provides latched data with a pipeline d e lay of 16 clock cycles. data outputs are available one propagation d e lay (t pd ) after the rising edge of the clock signal. minimize the length of the output data lines and loads placed on them to reduce transients within the AD9648 . these transients can degrade converter dynamic perfor m ance. the lowest typical conversion rate of the AD9648 is 10 msps. at clock rates below 10 msps, dynamic performance can d e grade. data clock output (dco) the ad96 48 provides two data clock output (dco) signals intended for capturing the data in an external regi s ter. in cmos output mode, the data outputs are valid on the rising edge of dco, unless the dco clock polarity has been changed via the spi. in lvds output mode, the dco and data output switching edges are closely aligned. additional delay can be added to the dco output using spi register 0x17 to increase the data setup time. in this case, the channel a output data is valid on the rising edge of dco, and the channel b output data is valid on the falling edge of dco. see figure 2 , figure 3 , and figure 4 for a graphical timing d e scripti on of the output modes. table 14 . output data format input (v) condition (v) offset binary output mode twos complement mode or vin+ ? vin? < ?vref ? 0.5 lsb 00 0000 0000 0000 10 0000 0000 0000 1 vin+ ? vin? = ?vref 00 000 0 0000 0000 10 0000 0000 0000 0 vin+ ? vin? = 0 10 0000 0000 0000 00 0000 0000 0000 0 vin+ ? vin? = +vref ? 1.0 lsb 11 1111 1111 1111 01 1111 1111 1111 0 vin+ ? vin? > +vref ? 0.5 lsb 11 1111 1111 1111 01 1111 1111 1111 1
AD9648 rev. 0 | page 32 of 44 built - in sel f- test (bist) and outp ut test the AD9648 includes a built - in test feature designed to enable verification of the integrity of each channel, as well as to facilitate board level debugging. a built - in self - test (bist) feature that verifies the integrity of the digital datapath of the AD9648 is included. various output test options are also provided to place predictable values on the outputs of the AD9648 . built - in self - test (bist) the bist is a thorough test of the digital portion of the selected AD9648 signal path. perform the bist test after a reset to ensure the part is in a known state. during bist, data from an internal pseudorandom noise ( pn) source is driven through the digital datapath of both channels, starting at the adc block output. at the datapath output, crc logic calculates a signature from the data. the bist sequ ence runs for 512 cycles and then stops. once completed, the bist compares t he signature results with a pre determined value. if the signatures match, the bist sets bit 0 of register 0x24, signifying the test passed. if the bist test fails, bit 0 of registe r 0x24 is cleared. the outputs are connected during this test, so the pn sequence can be observed as it runs. writing the value 0x05 to register 0x0e runs the bist. this enables bit 0 (bist enable) of register 0x0e and resets the pn sequence generator, bit 2 ( initialize bist sequence ) of register 0x0e. at the completion of the bist, bit 0 of register 0x24 is automatically cleared. the pn sequence can be continued from its last value by writing a 0 in bit 2 of register 0x0e. however, if the pn sequence is no t reset, the signature calculation does not equal the predetermined value at the end of the test. at that point, the user needs to rely on verifying the output data. output test modes the output test options are described in table 18 at address 0x0d . when an output test mode is enabled, the analog section of the adc is disconnected from the digital back - end blocks and the test pattern is run through the output formatting block. some of the test patterns are subject to output formatting, and some are not. the pn generators from the pn sequence tests can be reset by setting bit 4 or bit 5 of register 0x0d. these tests can be performed with or without an analog signal (if present, the analog signal is ignored), but the y do require an encode clock. for more information, see the an - 877 application note, interfacing to high speed adcs via spi .
AD9648 rev. 0 | page 33 of 44 serial port interfac e (spi) the AD9648 serial port interface (spi) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. th e spi gives the user added flexibility and customization , depending on the applicat ion. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields, which are docu - mented in the memory map secti on. for detailed operational information, see the an - 877 application note, interfacing to high speed adcs via spi . configuration using the spi three pins define the spi of this adc: the sclk/dfs pin, the sdio/d cs pin, and the csb pin (see table 15 ). the sclk/dfs (a serial clock) is used to synchronize the read and write data presented from and to the adc. the sdio/dcs (serial data input/output) is a dual - purpose pin that allows data to be sent to and read from the internal adc memory map registers. the csb (chip select bar) is an active low control that enables or disa bles the read and write cycles. table 15 . serial port interface pins pin function sclk serial c lock. the serial shift clock input, which is used to synchronize serial interface reads and writes. sdio serial data i np ut/o u tput. a dual - purpose pin that typically serves as an input or an output , depending on the instruction being sent a nd the relative position in the timing frame. csb chip select b ar. an active low control that gates the read and write cycles. the falling edge of the csb, in conjunction with the ris ing edge of the sclk, determine s the start of the framing. an exampl e of the serial timing and its definitions can be found in figure 62 and table 5 . other modes involving the csb are available. the csb can be held low indefinitely, which permanently enables the device; this is called streaming. the csb can stall high between bytes to allow for additional external timing. when csb is tied high, spi functions are placed in high impedance mode. this mode turns on any spi pin secondary functio ns. during an instruction phase, a 16 - bit instruction is transmitted. data follows the instruction phase, and its length is determined by the w0 and w1 bits. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on - chip memor y. the first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command i s issued. if the instruction is a readback operation, performing a readbac k causes the serial data input/ output (sdio) pin to change direction from an input to an output at the appropriate point in the serial frame. all data is composed of 8 - bit words. dat a can be sent in msb - first mode or in lsb - first mode. msb first is the default on power - up and can be changed via the spi port configuration register. for more information about this and other features, see the an - 877 application note, interfacing to high speed adcs via spi . don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 09975-046 figure 62 . serial port interface timing diagram
AD9648 rev. 0 | page 34 of 44 hardware interface the pins described in table 15 comprise the physi c al interface between the user programming device and the serial port of the AD9648 . the sclk pin and the csb pin function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in the an - 812 application note, micro - controller - based serial port interface (spi) boot circuit . the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk signal, the csb signal, and t he sdio signal are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9648 to prevent these signals from transi - tioning at the converter inputs during critical sampling periods. some pins serve a dual function when the spi interface is not being used. when the pins are strapped to dr vdd or ground d uring device power - on, they are associated with a specific function. table 16 describes the strappable functions supported on the AD9648 . configuration withou t the spi in applications that do not interface to the spi control registers, the sdio/dcs pin, the sclk/dfs pin, and the pdwn pin serve as standalone cmos - compatible control pins. when the device is powered up, it is assumed that the user intends to use the pins a s static control lines for the duty cycle stabilizer, out put data format, and power - down feature control. in this mode, the csb chip select bar should be connected to avdd, which disables the serial port interface. when the device i s in spi mode, the pdw n and oeb pins (if enabled) remain active. for spi control of output enable and power - down, the oeb and pdwn pins should be set to their default states. table 16 . mode selection pin external voltage configuration sdio/dcs dr vdd (de fault) duty cycle stabilizer enabled agnd duty cycle stabilizer dis abled sclk/dfs dr vdd twos comple ment enabled agnd (default) offset binary enabled oeb dr vdd outputs in high impedance agnd (default) outputs enabled pdwn dr vdd chip in power - down or standby agnd (default) normal operation spi accessible featu res table 17 provides a brief description of the general features that are accessible via the spi . these features are described in detail in the an - 877 application note, interfacing to high speed adcs via spi . the AD9648 part - specific features are described in detail following table 18 , the external memory map register table. table 17 . features accessible using the spi feature name description mode allows the user to set either power - down mode or standby mode clock allows the user to access the dcs, set the clock divider, set the clock divider phase, and enable the sync offset allows the user to digita lly adjust the converter offset test i/o allows the user to set test modes to have known data on output bits output mode allows the user to set the output mode including lvds output phase allows the user t o set the output clock polarity output delay allows the user to vary the dco delay
AD9648 rev. 0 | page 35 of 44 memory map reading the memory m ap register table each row in the memory map register table has eight bi t locations . the memory map is roughly divided into three sections: the chip configuration registers (address 0x00 to address 0x02); the channel index and tra nsfer registers (address 0x05 and address 0xff) and the adc functions registers , including setup, control, and test (ad dress 0 x08 to address 0x 1 0 2 ) . t he memory map register table (see table 18) list s the default hex adecimal value for each hexadecimal address shown. the column with the he ading bit 7 (msb) is the start of the default hexadecimal value given. for example, address 0x05, the d evice index register, has a hexadecimal default value of 0x03. this means that in address 0x05 bit s [7:2] = 0, and bits[1:0] = 1. this setting is a default channel index setti ng. the default value results in both adc channels receiving the next write command. for more information on this function and others, see the an - 877 application note, interfacing to high speed adcs via spi. th is application note details the functions controlled by register 0x00 to register 0xff. the remaining register s , are documented in the memory map register description section. open locations all address and bit locations that are not included in table 18 are not currently supported for this device. unused bits of a valid address location should be written with 0s. writing to these locations is required only when part of an address location is open (for example, addr ess 0x05 ). if the entire address location is open (for example, address 0x13), this address location should not be written to . default values after the AD9648 is reset, critical registers are loaded with defau lt values. the default values for the registers are given in the memory map register table, table 18. logic levels an explanatio n of logic level terminology follows: ? bit is set is synonymo us with bit is set to l ogic 1 or w riting logic 1 for the bit. ? cl ear a bit is synonymous with bit is set to logic 0 or w riting logic 0 for the bit. channel - specific registers some channel setup functions, such as the signal monitor thresholds, can be programmed differen tly for each channel. in these cases, channel address locations are internally duplicated for each channel. these registers and bits are designated in table 18 as local . these local registers and bits can be acce ssed by setting the appropriate channel a or channel b bits in register 0x05. if both bits are set, the subsequent write affects the registers of both channels. in a read cycle, only channel a or channel b should be set to read one of the two registers. i f both bits are set during an spi read cycle, the part returns the value for channe l a. registers and bits designated as global in table 18 affect the entire part or the channel features for which independent setti ngs are not allowed between channels.
AD9648 rev. 0 | page 36 of 44 memory map register table all address and bit locations that are not included in table 18 are not currently supported for this device. table 18 . memo ry map registers addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) comments chip configuration registers 0x00 spi port c onfig (g lobal) open lsb first soft reset 1 1 soft reset lsb first open 0x18 the nibbles are mirrored so lsb - first mode or msb - first mode registers correctly, regardless of shift mode 0x01 chip id (g lobal) 8 - bit c hip id [7:0] AD9648 = 0x 88 read only unique c hip id used to differentiate devices; read only 0x02 chip grade (global) open speed grade id 100 = 105 msps 101 = 125 msps open read only unique speed grade id used to differentiate devices; read only channel index and transfer registers 0x05 device i ndex (global) open open open open open open data channel b data channel a 0x03 bits are set to determine which device on the chip receives the next write command; applies to local registers only 0xff transfer (global) open open open open open open open transfer 0x00 synchron - ously transfers data from the master shift register to the slave adc functions 0x08 power m odes (local) open open external power - down pin functio n 0 = pdwn 1 = standby open open open internal power - down mode 00 = normal operation 01 = full power - down 10 = standby 11 = digital reset 0x 0 0 determines vario us generic modes of chip operation 0x09 global c lock (g lobal) open open open open open open open duty cycle stabilizer 0 = disabled 1 = e nabled 0x01
AD9648 rev. 0 | page 37 of 44 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) comments 0x0b clock d ivide (g lobal) open open open open open clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 the divide ratio is value plus 1 0x0c enhance - ment control (global) open open open open open chop 0 = disabled 1 = enabled open open 0x00 chop mode enabled if bit 2 is enabled 0x0d test m ode (local) user t est m ode c ontrol 00 = s ingle p attern m ode 01 = a lternate c ontinuous/ r epeat p attern m ode 10 = s ingle o nce p attern m ode 11 = a lternate o nce p attern m ode reset pn long gen reset pn short gen output test mode 0 000 = off (default) 0 001 = midscale short 0 010 = positive fs 0 011 = negative fs 0 100 = alternating checkerboard 0 101 = pn long sequence 0 110 = pn short sequence 0 111 = one/zero word toggle 1000 = user test mode 1111 = ramp output 0x00 w hen this register is set, the test data is placed on the output pins in place of normal data 0x0e bist e nable (g lobal ) open open open open open initialize bist sequence open bist enable 0x0 0 0x10 customer o ffset a djust (l ocal) offset adjust in lsbs from +127 to ?128 (twos complement format) 0x00 0x14 output mode output port logic type (global) 00 = cmos , 1.8 v 10 = lvds , ansi 11 = lvds , reduced r ange output interleave enable (global) output port disable (local) open (global) output invert (local) outp ut format 00 = offset binary 01 = twos complement 10 = g ray code 0x00 configures the outputs and the format of the data 0x15 output a djust open open cmos 1.8 v dco drive strength 00 = 1 01 = 2 10 = 3 11 = 4 open o pen cmos 1.8 v d ata drive strength 00 = 1 01 = 2 10 = 3 11 = 4 0x00 determines cmos output drive strength properties 0x16 clock phase control (global) invert dco clock 0 = not inverted 1 = inverted open open open open input clock divider phase adjust relative to the encode clock 000 = no delay 001 = one input clock cycle 010 = two input clock cycles 011 = three input clock cycles 100 = four input clock cycles 101 = five input clock cycles 110 = six input clock cycles 111 = seven input clock cycles 0x00 allows selection of clock delays into the input clock divider 0x17 output delay (global) dco c lock delay 0 = disabled 1 = enabled open data d elay 0 = disabled 1 = enabled open open delay s election 000 = 0.56 ns 001 = 1.12 ns 010 = 1.68 ns 011 = 2.24 ns 1 00 = 2.80 ns 101 = 3.36 ns 110 = 3.92 ns 111 = 4.48 ns 0x00 this sets the fine output delay of the output clock but does not change internal timing
AD9648 rev. 0 | page 38 of 44 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) comments 0x18 vref select (global) open open open open open internal v ref digital adjustment 000 = 1.0 v p - p 001 = 1 .14 v p - p 010 = 1.33 v p - p 011 = 1.6 v p - p 100 = 2.0 v p - p 0x 04 select and/ or adjust v ref 0x19 us er p attern 1 lsb (global) b7 b6 b5 b4 b3 b2 b1 b0 0x00 user - d efined pattern 1 lsb 0x1a user p attern 1 msb (global) b15 b14 b13 b12 b11 b10 b9 b8 0x00 user - defined p attern, 1 msb 0x1b u ser p attern 2 lsb (global) b7 b6 b5 b4 b3 b2 b1 b0 0x00 user - defined p attern 2 lsb 0x1c user p attern 2 msb b15 b14 b13 b12 b11 b10 b9 b8 0x00 user - defined p attern, 2 msb 0x24 misr lsb misr lsb [7:0] 0xff read only 0x25 misr msb misr msb [15:8] 0x ff read only 0x 2a over range control (global) open open open open open open open overrange output 0 = disabled 1 = enabled 0x0 1 over range control settings 0x2e output assign (local) open open open o pen open open open 0 = adc a 1 = adc b (local) adc a = 0x00 adc b = 0x01 assign an adc to an output channel 0x3a sync c ontrol (global) open open open open open sync next only sync enable open 0x00 sets the global sync options 0x100 sample rate override o pen s ample rate override enable resolution 010 = 14 bit s 100 = 12 bit s 110 = 10 bit s sample r ate 011 = 80 msps 100 = 105 msps 101 = 125 msps 0x00 0x101 user i/o control register 2 output e nable b ar (oeb) pin enable open open open open open open disable s dio pull - down 0x00 oeb and sdio pin controls 0x102 user i/o control register 3 open open open open vcm power - d own open 0x00
AD9648 rev. 0 | page 39 of 44 memory map register descriptions for additional information about functions controlled in register 0x00 to register 0xff, see the an - 877 application note, interfacing to high speed adcs via spi . power modes (register 0x08) bits open bit external power - down pin function if set, the external pdwn pin initiates power - down mode. if clear, the external pdwn pin initiates standby mode. bits[4:2] open bits[1:0] internal power - down mode in normal operation (bits[1:0] = 00), both adc channels are active. in power - down mode (bits[1:0] = 01), the digital data path clocks are disabled whi le the digital data path is reset. outputs are disabled . in standby mode (bits[1:0] = 10), the digital data path clocks and the outputs are disabled. during a digital reset (bits[1:0] = 11), the digital data path clocks are disabled while the digital data path is held in reset. the outputs are enabled in this state. for optimum performance, it is recom - mended that both adc channels be reset simultaneously. this is accomplished by ensuring that both channels are selected via register 0x05 prior to issuing th e digital reset instruction. enhancement control (register 0x0c) bits3 open bit 2 chop mode for applications that are sensitive to offset voltages and other low frequency noise, such as homodyne or direct - conversion receivers, chopping in the first sta ge of the ad9628 is a feature that can be enabled by setting bit 2. in the frequency domain, chopping translates offsets and other low frequency noise to f clk /2 where it can be filtered. bits[1:0] open output mode (register 0x14) bits output port logi c type 00 = cmos, 1.8 v 10 = lvds, ansi 11 = lvds, reduced range bit 5 output interleave enable for lvds outputs, setting bit 5 enables interleaving. channel a is sent coincident with a high dco clock, and channel b is coincident with a low dco clock. clea ring bit 5 disables the interleaving feature. channel a is sent on least significant bits (lsbs), and channel b is sent on most significant bits (msbs). the even bits are sent coincident with a high dco clock, and the odd bits are sent coincident with a low dco clock. for cmos outputs, setting bit 5 enables interleaving in cmos ddr mode. on adc output port a, channel a is sent coincident with a low dco clock , and channel b is coincident with a high dco clock. on adc output port b, channel b is sent coinci dent with a low dco clock , and channel a is coincident with a high dco clock. clearing bit 5 disables the interleaving feature, and data is output in cmos sdr mode. channel a is sent to port a, and channel b is sent to port b. bit 4 output port disable set ting bit 4 high disables the output port for the channels selected in bits[1:0] of the device index register (register 0x05). bit 3 open bit 2 output invert setting bit 2 high inverts the output port data for the channels selected in bits[1:0] of the devic e index register (register 0x05). bits[1:0] output format 00 = offset binary 01 = twos complement 10 = gray code sync control (register 0x 3a) bits3 open bit 2 clock divider ext sync only if the clock divider sync enable bit (address 0x3a, bit 1) is hi gh, bit 2 allows the clock divider to sync to the first sync pulse it receives and to ignore the rest. the clock divider sync enable bit resets after it syncs. bit 1 clock divider sync enable bit 1 gates the sync pulse to the clock divider. the sync signal is enabled when bit 1 is high. this is continuous sync mode. bit 0 open transfer (register 0xff) all registers except register 0x100 are updated the moment they are written. setting bit 0 of this transfer register high initializes the settings in the adc sample rate override register (address 0x100). sample rate override (register 0x100) this register is designed to allow the user to downgrade the device. any attempt to upgrade the default speed grade results in a chip power - down. settings in this register are not initialized until bit 0 of the transfer register (register 0xff) is written high.
AD9648 rev. 0 | page 40 of 44 user i/o control 2 (register 0x101) bit 7oeb pin enable if the oeb pin enable bit (bit 7) is set, the oeb pin is enabled. if bit 7 is clear, the oeb pin is disabled (default). bits[6:1]open bit 0sdio pull-down bit 0 can be set to disable the internal 30 k pull-down on the sdio pin, which can be used to limit the loading when many devices are connected to the spi bus. user i/o control 3 (register 0x102) bits[7:4]open bit 3vcm power-down bit 3 can be set high to power down the internal vcm generator. this feature is used when applying an external reference. bits[2:0]open
AD9648 rev. 0 | page 41 of 44 applications informa tion design guidelines before starting design and layout of the AD9648 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements that are needed for certain pins. power and groun d recommendations when connecting power to the AD9648 , it is recommended that two separate 1.8 v supplies be used. use o ne supply for analog (av dd) ; use a separate supply for the digital outputs (drvdd). for bo th av dd and d r vdd s everal different decoupling capa - citors should be used to cover both high and low frequencies. place t hese capacitors close to the point of entry at the pcb level and close to the pins of the part , with minimal trace length. a single pcb ground plane should be sufficient when using the AD9648 . with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. lvds operation the AD9648 defaults to cmos output mode on power - up. if lvds operation is desired , this mode must be programmed , using the spi configura tion registers after power - up. when the AD9648 powers up in cmos mode with l vds termination resistors (100 ? ) on the outputs , the drvdd current can be higher than the typical value until the pa rt is placed in lvds mode. this additional drvdd current does not cause damage to the AD9648 , but it should be taken into account when cons id - er ing the maximum drvdd current for the part. to avoid this additional drvdd current , the AD9648 outputs can be disabled at po wer - up by taking the pdwn pin high. after the part is placed into lvds mode via the spi port , the pdwn pin can be taken low to enable the outputs. exposed paddle thermal heat slug recommendations it is mandatory that the exposed paddle on the underside of the adc be connected to analog ground (agnd) to achieve the best electrical and thermal performance. a continuous, exposed (no solder mask) copper plane on the pcb should mate to the AD9648 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possible re sistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be filled or plugged to prevent solder wicking through the vias, which can compromise the connection . to maximize the coverage and adhesion between the adc a nd the pcb, a silkscreen should be overlaid to partition the continuous plane on the pcb into several uniform sections. this provides several tie points between the adc and the pcb during the reflow process. using one continuous plane with no partitions gu arantees only one tie point between the adc and the pcb. for detailed information about packaging and pcb layout of chip scale packages, see the an - 772 application note, a design and manufacturing guide for the lead frame chip scale package (lfcsp) , at www.analog.com . vcm the vcm pin should be decoupled to ground with a 0.1 f capacitor. reference decoupling the vref pin should be externally decoupled to ground with a low esr , 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. spi port the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk, csb, and sdio signals are typic ally asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9648 to keep these signals from transitioning at the converter inputs during critical sampling periods.
AD9648 rev. 0 | page 42 of 44 outline dimensions compliant to jedec standards mo-220-vmmd-4 091707-c 6.35 6.20 sq 6.05 0.25 min t o p view 8.75 bsc sq 9.00 bsc sq 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 ty p 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max exposed pad (bottom view) sea ting plane pin 1 indic a t or pin 1 indic a t or 0.30 0.23 0.18 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 63 . 64 - lead lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad (cp - 64 - 4) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9648bcpz -105 ?4 0c to +85c 64- lead lead f rame chip scale package [lfcsp_ v q] cp -64-4 AD9648bcpz -125 ?4 0c to +85c 64- lead lead f rame chip scale package [lfcsp_ v q] cp -64-4 AD9648bcpzrl7 - 10 5 ?4 0c to +85c 64- lead lead f rame chip scale package [lfcsp_ v q] cp -64-4 AD9648bcpzrl7 - 125 ?4 0c to +85c 64- lead lead f rame chip scale package [lfcsp_ v q] cp -64-4 AD9648 - 125 ebz evaluation board 1 z = rohs compliant part.
AD9648 rev. 0 | page 43 of 44 not es
AD9648 rev. 0 | page 44 of 44 notes ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09975 - 0 - 7/11(0)

▲Up To Search▲

Price & Availability of AD9648

	To Download AD9648 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .